MIM capacitor

ABSTRACT

At present, Cu (copper) is being used as a wiring material. In an RF-CMOS device as a combination of an RF analog device and CMOS logic device, two electrodes of a MIM capacitor are formed from Cu having a large diffusion coefficient. To prevent Cu from diffusing to the capacitor insulating film of the MIM capacitor, diffusion prevention films having a function of preventing diffusion of Cu are interposed between the capacitor insulating film and the two electrodes. As a result, Cu forming the electrodes does not diffuse to the capacitor insulating film.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Applications No. 11-354473, filed Dec.14, 1999; No. 2000-368693, filed Dec. 4, 2000, the entire contents ofwhich are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a MIM (Metal-Insulator-Metal)capacitor.

[0003] In recent years, for example, the plausibility of forming an RFanalog device and CMOS logic device on one chip is being examined. TheRF analog device includes a resistor, coil, and capacitor, whereas theCMOS logic device is formed from a MOS transistor.

[0004] To form an RF analog device and CMOS logic device on one chip,the manufacturing processes of these devices must be integrated. Forexample, the process of the RF analog device is integrated based on theCMOS logic process to develop a new RF-CMOS process.

[0005] The first problem in integrating the processes is the structureand process of a MIM capacitor. For example, when the gate length of aMOS transistor is 0.1 μm or less, the use of Cu (copper) as a wiringmaterial is examined to reduce the wiring resistance and the like.

[0006] However, Cu has a large diffusion coefficient. When, therefore, aMIM capacitor having a Cu electrode is formed, Cu diffuses into acapacitor insulating film to increase the leakage current.

[0007] When Cu is used as a wiring material, a Cu wiring line is formedby a so-called damascene process because of the processing precision andflatness. At this time, the electrode of the MIM capacitor is alsoformed by the damascene process, and thus suffers problems caused by thedamascene process, e.g., dishing and reduction in electrode area inavoiding dishing.

BRIEF SUMMARY OF THE INVENTION

[0008] It is an object of the present invention to provide amanufacturing process for satisfactorily preventing the leakage currenteven when the electrode of a MIM capacitor is formed from a materialsuch as Cu having a large diffusion coefficient, and avoiding dishingand reduction in electrode area even when the damascene process (CMPprocess) is employed.

[0009] A MIM capacitor according to the present invention comprisesfirst and second electrodes formed from a metal material, a capacitorinsulating film, a first diffusion prevention film interposed betweenthe capacitor insulating film and the first electrode to preventdiffusion of the metal material, and a second diffusion prevention filminterposed between the capacitor insulating film and the secondelectrode to prevent diffusion of the metal material.

[0010] A manufacturing method of a MIM capacitor according to thepresent invention comprises the steps of forming a first electrode froma metal material by a damascene process, forming on the first electrodea first insulating film having a function of preventing diffusion of themetal material, removing part of the first insulating film to use thepart as a capacitor area, forming in the capacitor area a firstdiffusion prevention film having a function of preventing diffusion ofthe metal material, forming on the first diffusion prevention film acapacitor insulating film, a second diffusion prevention film having afunction of preventing diffusion of the metal material, and a secondinsulating film having the same function as the first insulating film,forming an interlevel insulating film on the first and second insulatingfilms, forming using the damascene process trenches reaching the firstelectrode and the second diffusion prevention film in the interlevelinsulating film and the first and second insulating films, and fillingthe metal material in the trenches to form a wiring line connected tothe first electrode and a second electrode connected to the seconddiffusion prevention film.

[0011] Additional objects and advantages of the invention will be setforth in the description which follows, and in part will be obvious fromthe description, or may be learned by practice of the invention. Theobjects and advantages of the invention may be realized and obtained bymeans of the instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0012] The accompanying drawings, which are incorporated in andconstitute a part of the specification, illustrate presently preferredembodiments of the invention, and together with the general descriptiongiven above and the detailed description of the preferred embodimentsgiven below, serve to explain the principles of the invention.

[0013]FIG. 1 is a plan view showing the first embodiment of a MIMcapacitor according to the present invention;

[0014]FIG. 2 is a sectional view taken along the line II-II in FIG. 1;

[0015]FIG. 3 is a plan view showing one step in manufacturing a devicein FIGS. 1 and 2;

[0016]FIG. 4 is a sectional view taken along the line IV-IV in FIG. 3;

[0017]FIG. 5 is a plan view showing a layout example of the firstelectrode of the capacitor;

[0018]FIG. 6 is a plan view showing another layout example of the firstelectrode of the capacitor;

[0019]FIG. 7 is a plan view showing still another layout example of thefirst electrode of the capacitor;

[0020]FIG. 8 is a plan view showing another step in manufacturing thedevice in FIGS. 1 and 2;

[0021]FIG. 9 is a sectional view taken along the line IX-IX in FIG. 8;

[0022]FIG. 10 is a plan view showing still another step in manufacturingthe device in FIGS. 1 and 2;

[0023]FIG. 11 is a plan view showing still another step in manufacturingthe device in FIGS. 1 and 2;

[0024]FIG. 12 is a sectional view taken along the line XII-XII in FIG.11;

[0025]FIG. 13 is a plan view showing a layout example of the secondelectrode of the capacitor;

[0026]FIG. 14 is a plan view showing another layout example of thesecond electrode of the capacitor;

[0027]FIG. 15 is a plan view showing still another layout example of thesecond electrode of the capacitor;

[0028]FIG. 16 is a sectional view showing the second embodiment of a MIMcapacitor according to the present invention;

[0029]FIG. 17 is a sectional view showing one step in manufacturing adevice in FIG. 16;

[0030]FIG. 18 is a sectional view showing another step in manufacturingthe device in FIG. 16;

[0031]FIG. 19 is a sectional view showing still another step inmanufacturing the device in FIG. 16;

[0032]FIG. 20 is a sectional view showing still another step inmanufacturing the device in FIG. 16;

[0033]FIG. 21 is a sectional view showing the third embodiment of a MIMcapacitor according to the present invention;

[0034]FIG. 22 is a sectional view showing one step in manufacturing adevice in FIG. 21;

[0035]FIG. 23 is a sectional view showing another step in manufacturingthe device in FIG. 21;

[0036]FIG. 24 is a sectional view showing still another step inmanufacturing the device in FIG. 21;

[0037]FIG. 25 is a sectional view showing still another step inmanufacturing the device in FIG. 21;

[0038]FIG. 26 is a sectional view showing still another step inmanufacturing the device in FIG. 21;

[0039]FIG. 27 is a plan view showing a layout example of the secondelectrode of the capacitor;

[0040]FIG. 28 is a sectional view showing the fourth embodiment of a MIMcapacitor according to the present invention;

[0041]FIG. 29 is a sectional view showing one step in manufacturing adevice in FIG. 28;

[0042]FIG. 30 is a sectional view showing another step in manufacturingthe device in FIG. 28;

[0043]FIG. 31 is a sectional view showing still another step inmanufacturing the device in FIG. 28;

[0044]FIG. 32 is a sectional view showing still another step inmanufacturing the device in FIG. 28;

[0045]FIG. 33 is a sectional view showing still another step inmanufacturing the device in FIG. 28;

[0046]FIG. 34 is a sectional view showing the fifth embodiment of a MIMcapacitor according to the present invention;

[0047]FIG. 35 is a plan view showing one step in manufacturing a devicein FIG. 34;

[0048]FIG. 36 is a sectional view taken along the line XXXVI-XXXVI inFIG. 35;

[0049]FIG. 37 is a sectional view showing another step in manufacturingthe device in FIG. 34;

[0050]FIG. 38 is a sectional view showing still another step inmanufacturing the device in FIG. 34;

[0051]FIG. 39 is a sectional view showing still another step inmanufacturing the device in FIG. 34;

[0052]FIG. 40 is a plan view showing a layout example of the secondelectrode of the capacitor;

[0053]FIG. 41 is a sectional view showing the sixth embodiment of a MIMcapacitor according to the present invention;

[0054]FIG. 42 is a sectional view showing the seventh embodiment of aMIM capacitor according to the present invention;

[0055]FIG. 43 is a sectional view taken along the line XLIII-XLIII inFIG. 42;

[0056]FIG. 44 is a sectional view showing the eighth embodiment of a MIMcapacitor according to the present invention; and

[0057]FIG. 45 is a sectional view showing the ninth embodiment of a MIMcapacitor according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0058] A MIM capacitor of the present invention will be described belowin detail with reference to the accompanying drawing.

[0059]FIG. 1 is a sectional view showing the first embodiment of a MIMcapacitor according to the present invention. FIG. 2 is a sectional viewtaken along the line II-II in FIG. 1.

[0060] For example, a matrix-like trench is formed in a semiconductorsubstrate (e.g., silicon substrate) 11. The trench is filled with ametal material 12, e.g., Cu (copper) having a low resistance and largediffusion coefficient. The metal material 12 filled in the trench of thesemiconductor substrate 11 serves as the first electrode of the MIMcapacitor.

[0061] The first embodiment adopts a matrix shape as the layout of thefirst electrode of the MIM capacitor in order to prevent dishing(phenomenon that a metal material in a trench is polished like a dish)in the damascene process (CMP process). As far as the structure canprevent dishing, the trench shape is not limited to the matrix shape,and may be a drainboard (or ladder) or comb shape.

[0062] A silicon nitride film (SiN) 13 is formed on the semiconductorsubstrate 11 except for the capacitor area of the MIM capacitor. Thecapacitor area of the MIM capacitor is a groove surrounded by the wallof the silicon nitride film 13. In the capacitor area, a tungstennitride film (WN) 14 is formed. The tungsten nitride film 14 functionsas a diffusion prevention film against the metal material (e.g., Cu) 12.At the same time, the tungsten nitride film 14 is formed on thematrix-like first electrode to increase the capacitor area.

[0063] A capacitor insulating film (e.g., Ta₂O₅) 15 is formed on thetungsten nitride film 14.

[0064] A tungsten nitride film (WN) 16 is formed on the capacitorinsulating film 15. The tungsten nitride film 16 functions as adiffusion prevention film against a metal material (e.g., Cu) serving asthe second electrode (to be described later) of the MIM capacitor. Inaddition, the tungsten nitride film 16 is formed below the matrix-likesecond electrode (to be described later) to increase the capacitor area.

[0065] A silicon nitride film (SiN) 17 is formed on the tungsten nitridefilm 16. The silicon nitride film 17 functions as a stopper togetherwith the silicon nitride film 13 in etching (in trench formation)(details of which will be explained in a description of themanufacturing method).

[0066] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilms 13 and 17, and a silicon nitride film 19 is formed on the siliconoxide film 18. The silicon nitride film 19 functions as a stopper intrench formation by the dual damascene process. A silicon oxide film(SiO₂) 20 is formed on the silicon nitride film 19, and a siliconnitride film 21 is formed on the silicon oxide film 20. The siliconnitride film 21 functions as a stopper in the CMP (Chemical MechanicalPolishing) process.

[0067] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches (via holes) reaching the tungstennitride film 16 and metal material (e.g., Cu) 12 are formed in thesilicon oxide film 18 and silicon nitride film 13. These trenches arefilled with metal materials 22A and 22B, e.g., Cu (copper) having a lowresistance and large diffusion coefficient. The metal material 22Afilled in the trench serves as the second electrode of the MIMcapacitor.

[0068] The first embodiment adopts a matrix shape as the layout of thesecond electrode of the MIM capacitor in order to prevent dishing in thedamascene process (CMP process). As far as the structure can preventdishing, the trench shape is not limited to the matrix shape, and may bea drainboard (or ladder) or comb shape.

[0069] In this device structure, the first and second electrodes of theMIM capacitor are formed into a shape such as a matrix, drainboard, orcomb shape in which dishing hardly occurs.

[0070] When the first and second electrodes of the MIM capacitor aremade of a metal material (e.g., Cu) having a large diffusioncoefficient, a plate-like diffusion prevention film (e.g., tungstennitride film 14) in contact with the first electrode, and a plate-likediffusion prevention film (e.g., tungsten nitride film 16) in contactwith the second electrode are formed. These diffusion prevention filmsalso increase the capacitor area of the MIM capacitor.

[0071] The capacitor insulating film (e.g., Ta₂O₅) 15 is sandwichedbetween the two diffusion prevention films, and does not directlycontact the metal material (e.g., Cu) having a large diffusioncoefficient.

[0072] The leakage current can be reduced without contaminating thecapacitor insulating film by the metal material which has a largediffusion coefficient and forms the electrode of the MIM capacitor. As aresult, a high-performance MIM capacitor can be provided.

[0073] The manufacturing method of the MIM capacitor in FIGS. 1 and 2will be explained.

[0074] As shown in FIGS. 3 and 4, the first electrode of a MIM capacitoris formed in a semiconductor substrate 11 by the damascene process.

[0075] For example, a matrix-like trench is formed in the semiconductorsubstrate 11 using PEP (Photo Engraving Process) and RIE (Reactive IonEtching). A metal material (e.g., Cu) 12 for completely filling thematrix-like trench is formed using CVD (Chemical Vapour Deposition).Then, the metal material 12 is polished using CMP (Chemical MechanicalPolishing) to leave it in only the matrix-like trench, therebycompleting the first electrode of the MIM capacitor.

[0076] The shape of the trench (first electrode) may be a drainboardshape as shown in FIG. 5, or a comb shape as shown in FIG. 6 or 7 inaddition to the matrix shape.

[0077] A silicon nitride film (diffusion prevention insulating film) 13for covering the first electrode of the MIM capacitor is formed on thesemiconductor substrate 11 using CVD.

[0078] As shown in FIGS. 8 and 9, the silicon nitride film 13 present inthe capacitor area is removed using PEP and RIE. A tungsten nitride film(WN) 14 as a diffusion prevention film is formed on the silicon nitridefilm 13 and in the capacitor area using sputtering. The tungsten nitridefilm 14 is polished using CMP to leave it in only the capacitor area.

[0079] Note that the first embodiment uses the tungsten nitride film asa diffusion prevention film (barrier metal), but may use a film otherthan the tungsten nitride film so long as the film has a metal atomdiffusion prevention function. For example, materials as shown in Table1 are known as a conductive film having the diffusion preventionfunction. TABLE 1 Diffusion-resistant Film thickness (° C.) (nm) Crystalstructure Ti 450 220 Polycrystalline TiN 600 50 Polycrystalline TiSiN600 30 Amorphous Ta 500 50 Polycrystalline TaN 700 8 Polycrystalline TaC600 5 Amorphous TaSiN 900 120 Amorphous TaCeO₂ 850 10 PolycrystallineIr₄₆Ta₅₄ 700 30 Amorphous W 450 100 Polycrystalline WN 700 120Polycrystalline W₂N 600 8 Amorphous W₆₄B₂₀N₁₆ 800 100 PolycrystallineW₂₃B₄₉N₂₈ 700 100 Amorphous W₄₇Si₉N₄₄ 700 100 Amorphous

[0080] As shown in FIG. 10, a capacitor insulating film (e.g., Ta₂O₅) 15is formed on the silicon nitride film 13 and tungsten nitride film 14using sputtering. A tungsten nitride film 16 as a diffusion preventionfilm (barrier metal) is formed on the capacitor insulating film 15 usingsputtering. As the diffusion prevention film, conductive films as shownin Table 1 can be used in addition to the tungsten nitride film.

[0081] A silicon nitride film (diffusion prevention insulating film) 17is formed on the tungsten nitride film 16 using CVD. The silicon nitridefilm 17, tungsten nitride film 16, and capacitor insulating film 15 aresequentially etched using PEP and RIE. Etching is performed such thatthe capacitor insulating film 15, tungsten nitride film 16, and siliconnitride film 17 remain on the tungsten nitride film 14 in at least thecapacitor area.

[0082] As shown in FIGS. 11 and 12, a silicon oxide film (interlevelinsulating film) 18 is formed on the silicon nitride films 13 and 17using CVD. Subsequently, a silicon nitride film 19 as an etching stopperis formed on the silicon oxide film 18 using CVD. A silicon oxide film(inter-wiring insulating film) 20 is formed on the silicon nitride film19 using CVD. A silicon nitride film 21 as a CMP stopper is formed onthe silicon oxide film 20 using CVD.

[0083] After that, the second electrode of the MIM capacitor is formedby the dual damascene process.

[0084] For example, a trench as a wiring groove is formed in the siliconnitride film 21 and silicon oxide film 20 using PEP and RIE. In etchingthe silicon oxide film 20, the silicon nitride film 19 functions as aRIE etching stopper. The trench includes a wiring/pad portion andcapacitor electrode portion, and the capacitor electrode portion has,e.g., a matrix-like layout.

[0085] Then, trenches as via holes are formed in the silicon nitridefilm 19 and silicon oxide film 18 using PEP and RIE. In etching thesilicon oxide film 18, the silicon nitride films 13 and 17 function asRIE etching stoppers.

[0086] Note that the trench shape at the capacitor electrode portion isnot limited to the matrix shape, and may be, e.g., a drainboard shape asshown in FIG. 13, or a comb shape as shown in FIG. 14 or 15.

[0087] The silicon nitride films 13 and 17 at the bottoms of thetrenches are etched to expose part of the metal material 12 and part ofthe tungsten nitride film 16.

[0088] Thereafter, metal materials (e.g., Cu) 22A and 22B for completelyfilling the trenches are formed by plating. Note that a barrier metalsuch as TaN may be formed on the inner surface of the trench before themetal materials 22A and 22B are formed.

[0089] The metal materials 22A and 22B are polished using CMP to leavethem in the trenches. At this time, the silicon nitride film 21functions as a CMP stopper.

[0090] By these steps, the MIM capacitor in FIGS. 1 and 2 is completed.

[0091] According to this manufacturing method, when the damasceneprocess (CMP process) is adopted, and a metal material such as Cu(copper) having a large diffusion coefficient is used as a wiringmaterial, first, the metal material (capacitor electrode) can be formedinto, e.g., a matrix shape to prevent dishing. Second, a capacitorinsulating film can be directly sandwiched between diffusion preventionfilms to prevent metal atoms from diffusing into the capacitorinsulating film during the manufacturing process. Third, the diffusionprevention film functions as a capacitor electrode, so the capacitorarea does not decrease (capacitor capacity can be increased regardlessof the wiring rule) even if the metal material is formed into a matrixshape in order to prevent dishing. Fourth, the metal material (e.g., Cu)is not exposed in patterning the capacitor, so that contamination bymetal atoms can be avoided. Fifth, the capacitor structure is flat, andhigh reliability and high performance can be achieved.

[0092]FIG. 16 shows the second embodiment of a MIM capacitor accordingto the present invention.

[0093] Compared to the embodiment in FIGS. 1 and 2, the device structureof the second embodiment is characterized by the absence of the siliconnitride film 13 in FIGS. 1 and 2. In other words, in the secondembodiment, a silicon nitride film 17 is formed not only on a tungstennitride film 16 but also on a semiconductor substrate 11 and metalmaterial 12.

[0094] The detailed structure will be explained.

[0095] For example, a matrix-like trench is formed in a semiconductorsubstrate (e.g., silicon substrate) 11. The trench is filled with ametal material 12, e.g., Cu (copper) having a low resistance and largediffusion coefficient. The metal material 12 filled in the trench of thesemiconductor substrate 11 serves as the first electrode of the MIMcapacitor.

[0096] Note that the shape of the first electrode of the MIM capacitoris set to a matrix shape, drainboard shape (or ladder shape), combshape, or the like.

[0097] A tungsten nitride film (WN) 14 is formed in the capacitor areaof the MIM capacitor. The tungsten nitride film 14 functions as adiffusion prevention film against the metal material (e.g., Cu) 12. Atthe same time, the tungsten nitride film 14 is formed on the matrix-likefirst electrode to increase the capacitor area. A capacitor insulatingfilm (e.g., Ta₂O₅) 15 is formed on the tungsten nitride film 14.

[0098] A tungsten nitride film (WN) 16 is formed on the capacitorinsulating film 15. The tungsten nitride film 16 functions as adiffusion prevention film against a metal material (e.g., Cu) serving asthe second electrode (to be described later) of the MIM capacitor. Inaddition, the tungsten nitride film 16 is formed below the matrix-likesecond electrode (to be described later) to increase the capacitor area.

[0099] A silicon nitride film (SiN) 17 is formed on the semiconductorsubstrate 11, metal material 12, and tungsten nitride film 16. Thesilicon nitride film 17 functions as a stopper in etching (in trenchformation) (details of which will be explained in a description of themanufacturing method).

[0100] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilm 17, and a silicon nitride film 19 is formed on the silicon oxidefilm 18. The silicon nitride film 19 functions as a stopper in trenchformation by the dual damascene process. A silicon oxide film (SiO₂) 20is formed on the silicon nitride film 19, and a silicon nitride film 21is formed on the silicon oxide film 20. The silicon nitride film 21functions as a stopper in the CMP (Chemical Mechanical Polishing)process.

[0101] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches as via holes reaching the tungstennitride film 16 and metal material (e.g., Cu) 12 are formed in thesilicon oxide film 18 and silicon nitride film 17. These trenches arefilled with metal materials 22A and 22B, e.g., Cu (copper) having a lowresistance and large diffusion coefficient. The metal material 22Afilled in the trench serves as the second electrode of the MIMcapacitor.

[0102] Note that the shape of the second electrode of the MIM capacitoris set to a matrix shape, drainboard shape (or ladder shape), combshape, or the like.

[0103] In this device structure, the first and second electrodes of theMIM capacitor are formed into a shape such as a matrix, drainboard, orcomb shape in which dishing hardly occurs.

[0104] When the first and second electrodes of the MIM capacitor aremade of a metal material (e.g., Cu) having a large diffusioncoefficient, a plate-like diffusion prevention film (e.g., tungstennitride film 14) in contact with the first electrode, and a plate-likediffusion prevention film (e.g., tungsten nitride film 16) in contactwith the second electrode are formed. These diffusion prevention filmsalso increase the capacitor area of the MIM capacitor.

[0105] The capacitor insulating film (e.g., Ta₂O₅) 15 is sandwichedbetween the two diffusion prevention films, and does not directlycontact the metal material (e.g., Cu) having a large diffusioncoefficient.

[0106] The leakage current can be reduced without contaminating thecapacitor insulating film by the metal material which has a largediffusion coefficient and forms the electrode of the MIM capacitor.Thus, a high-performance MIM capacitor can be provided.

[0107] The second embodiment uses only the silicon nitride film 17 as enetching stopper in forming a trench (via hole) in the silicon oxide film18, and eliminates the silicon nitride film 13 of the device as shown inFIGS. 1 and 2. Compared to the embodiment in FIGS. 1 and 2, the secondembodiment can omit {circle over (1)} the step of processing the siliconnitride film 13 and {circle over (2)} the step (CMP) of burying thetungsten nitride film 14 in the groove of the silicon nitride film 13,thereby decreasing the number of PEP steps and reducing the cost.

[0108] The manufacturing method of the MIM capacitor in FIG. 16 will beexplained.

[0109] As shown in FIG. 17, the first electrode of a MIM capacitor isformed in a semiconductor substrate 11 by the damascene process.

[0110] For example, a matrix-like trench is formed in the semiconductorsubstrate 11 using PEP and RIE. A metal material (e.g., Cu) 12 forcompletely filling the matrix-like trench is formed using CVD. The metalmaterial 12 is polished using CMP to leave it in only the matrix-liketrench, thereby completing the first electrode of the MIM capacitor.

[0111] The shape of the trench (first electrode) may be a drainboardshape (FIG. 5), or comb shape (FIG. 6 or 7) in addition to the matrixshape as shown in FIG. 3.

[0112] A tungsten nitride film (WN) 14 as a diffusion prevention film isformed on the semiconductor substrate 11 and metal material 12 usingsputtering. Note that the second embodiment uses the tungsten nitridefilm as a diffusion prevention film (barrier metal), but may use a filmother than the tungsten nitride film so long as the film has a metalatom diffusion prevention function (see Table 1).

[0113] A capacitor insulating film (e.g., Ta₂O₅) 15 is formed on thetungsten nitride film 14 using sputtering. A tungsten nitride film 16 asa diffusion prevention film (barrier metal) is formed on the capacitorinsulating film 15 using sputtering.

[0114] As shown in FIG. 18, the tungsten nitride film 16, capacitorinsulating film 15, and tungsten nitride film 14 are sequentially etchedusing PEP and RIE. As a result, the tungsten nitride film 14, capacitorinsulating film 15, and tungsten nitride film 16 remain in only thecapacitor area.

[0115] As shown in FIG. 19, a silicon nitride film (diffusion preventioninsulating film) 17 is formed on the semiconductor substrate 11, metalmaterial 12, and tungsten nitride film 16 using CVD. The silicon nitridefilm 17 functions as a stopper in forming trenches as via holes (to bedescribed later).

[0116] As shown in FIG. 20, a silicon oxide film (interlevel insulatingfilm) 18 is formed on the silicon nitride film 17 using CVD. Then, asilicon nitride film 19 as an etching stopper is formed on the siliconoxide film 18 using CVD. A silicon oxide film (inter-wiring insulatingfilm) 20 is formed on the silicon nitride film 19 using CVD. A siliconnitride film 21 as a CMP stopper is formed on the silicon oxide film 20using CVD.

[0117] Thereafter, the second electrode of the MIM capacitor is formedby the dual damascene process.

[0118] For example, a trench as a wiring groove is formed in the siliconnitride film 21 and silicon oxide film 20 using PEP and RIE. In etchingthe silicon oxide film 20, the silicon nitride film 19 functions as aRIE etching stopper. The trench includes a wiring/pad portion andcapacitor electrode portion, and the capacitor electrode portion has,e.g., a matrix-like layout.

[0119] Then, trenches as via holes are formed in the silicon nitridefilm 19 and silicon oxide film 18 using PEP and RIE. In etching thesilicon oxide film 18, the silicon nitride film 17 functions as a RIEetching stopper.

[0120] Note that the trench shape at the capacitor electrode portion isnot limited to the matrix shape, and may be, e.g., a drainboard shape asshown in FIG. 13, or a comb shape as shown in FIG. 14 or 15.

[0121] The silicon nitride film 17 at the bottom of the trench is etchedto expose part of the metal material 12 and part of the tungsten nitridefilm 16.

[0122] Metal materials (e.g., Cu) 22A and 22B for completely filling thetrenches are formed by plating. Note that a barrier metal such as TaNmay be formed on the inner surface of the trench before the metalmaterials 22A and 22B are formed.

[0123] The metal materials 22A and 22B are polished using CMP to leavethem in only the trench. At this time, the silicon nitride film 21functions as a CMP stopper.

[0124] By these steps, the MIM capacitor in FIG. 16 is completed.

[0125] According to this manufacturing method, when the damasceneprocess (CMP process) is adopted, and a metal material such as Cu(copper) having a large diffusion coefficient is used as a wiringmaterial, first, the metal material (capacitor electrode) can be formedinto, e.g., a matrix shape to prevent dishing. Second, diffusionprevention films which directly sandwich the capacitor insulating filmcan be formed to prevent metal atoms from diffusing into a capacitorinsulating film during the manufacturing process. Third, the diffusionprevention film functions as a capacitor electrode, so the capacitorarea does not decrease (capacitor capacity can be increased regardlessof the wiring rule) even if the metal material is formed into a matrixshape in order to prevent dishing. Fourth, only one silicon nitride filmis used as a stopper in forming trenches as via holes, which candecrease the number of PEP steps and reduce the cost.

[0126]FIG. 21 shows the third embodiment of a MIM capacitor according tothe present invention.

[0127] Compared to the embodiment in FIGS. 1 and 2, the device structureof the third embodiment is characterized by the layout of a tungstennitride film 14 serving as a diffusion prevention film. Morespecifically, in this embodiment, the tungsten nitride film 14 as adiffusion prevention film is etched subsequently to etching of a siliconnitride film 17, tungsten nitride film 16, and capacitor insulating film15. The device structure of this embodiment has a layout in which theends of the tungsten nitride films 14 and 16, and capacitor insulatingfilm 15 overlap a silicon nitride film 13.

[0128] Accordingly, the third embodiment can eliminate the step (CMP) offilling the tungsten nitride film 14 in the groove of the siliconnitride film 13 shown in the embodiment of FIGS. 1 and 2.

[0129] The detailed device structure will be explained.

[0130] For example, a matrix-like trench is formed in a semiconductorsubstrate (e.g., silicon substrate) 11. The trench is filled with ametal material 12, e.g., Cu (copper) having a low resistance and largediffusion coefficient. The metal material 12 filled in the trench of thesemiconductor substrate 11 serves as the first electrode of the MIMcapacitor.

[0131] The shape of the first electrode of the MIM capacitor is set to,e.g., a matrix, drainboard (or ladder), or comb shape.

[0132] A silicon nitride film (SiN) 13 is formed on the semiconductorsubstrate 11 except for the capacitor area of the MIM capacitor. Thecapacitor area of the MIM capacitor is a groove surrounded by the wallof the silicon nitride film 13. In the capacitor area, a tungstennitride film (WN) 14 is formed. The end of the tungsten nitride film 14overlaps the silicon nitride film 13.

[0133] The tungsten nitride film 14 functions as a diffusion preventionfilm against the metal material (e.g., Cu) 12. At the same time, thetungsten nitride film 14 is formed on the matrix-like first electrode toincrease the capacitor area. A capacitor insulating film (e.g., Ta₂O₅)15 is formed on the tungsten nitride film 14.

[0134] A tungsten nitride film (WN) 16 is formed on the capacitorinsulating film 15. The tungsten nitride film 16 functions as adiffusion prevention film against a metal material (e.g., Cu) serving asthe second electrode (to be described later) of the MIM capacitor. Inaddition, the tungsten nitride film 16 is formed below the matrix-likesecond electrode (to be described later) to increase the capacitor area.

[0135] A silicon nitride film (SiN) 17 is formed on the tungsten nitridefilm 16. The silicon nitride film 17 functions as a stopper togetherwith the silicon nitride film 13 in etching (in trench formation)(details of which will be explained in a description of themanufacturing method).

[0136] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilms 13 and 17, and a silicon nitride film 19 is formed on the siliconoxide film 18. The silicon nitride film 19 functions as a stopper intrench formation by the dual damascene process. A silicon oxide film(SiO₂) 20 is formed on the silicon nitride film 19, and a siliconnitride film 21 is formed on the silicon oxide film 20. The siliconnitride film 21 functions as a stopper in the CMP (Chemical MechanicalPolishing) process.

[0137] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches (via holes) reaching the tungstennitride film 16 and metal material (e.g., Cu) 12 are formed in thesilicon oxide film 18 and silicon nitride film 13. These trenches arefilled with metal materials 22A and 22B, e.g., Cu (copper) having a lowresistance and large diffusion coefficient. The metal material 22Afilled in the trench serves as the second electrode of the MIMcapacitor.

[0138] The second electrode of the MIM capacitor can be formed into to,e.g., a shape as shown in FIG. 27. However, any shape can be employed asfar as dishing in the damascene process (CMP process) can be prevented.

[0139] In this device structure, the first and second electrodes of theMIM capacitor are formed into a shape such as a matrix, drainboard (orladder), or comb shape in which dishing hardly occurs.

[0140] When the first and second electrodes of the MIM capacitor aremade of a metal material (e.g., Cu) having a large diffusioncoefficient, a plate-like diffusion prevention film (e.g., tungstennitride film 14) in contact with the first electrode, and a plate-likediffusion prevention film (e.g., tungsten nitride film 16) in contactwith the second electrode are formed. These diffusion prevention filmsalso increase the capacitor area of the MIM capacitor.

[0141] The capacitor insulating film (e.g., Ta₂O₅) 15 is sandwichedbetween the two diffusion prevention films, and does not directlycontact the metal material (e.g., Cu) having a large diffusioncoefficient.

[0142] The leakage current can be reduced without contaminating thecapacitor insulating film by the metal material which has a largediffusion coefficient and forms the electrode of the MIM capacitor. As aresult, a high-performance MIM capacitor can be provided.

[0143] The manufacturing method of the MIM capacitor in FIG. 21 will beexplained.

[0144] As shown in FIG. 22, the first electrode of a MIM capacitor isformed in a semiconductor substrate 11 by the damascene process.

[0145] For example, a matrix-like trench is formed in the semiconductorsubstrate 11 using PEP (Photo Engraving Process) and RIE (Reactive IonEtching). A metal material (e.g., Cu) 12 for completely filling thematrix-like trench is formed using CVD. Then, the metal material 12 ispolished using CMP to leave it in only the matrix-like trench, therebycompleting the first electrode of the MIM capacitor.

[0146] Note that the shape of the trench (first electrode) is set to amatrix shape (FIG. 3), drainboard shape (FIG. 5), comb shape (FIG. 6 or7), or the like.

[0147] A silicon nitride film (diffusion prevention insulating film) 13for covering the first electrode of the MIM capacitor is formed on thesemiconductor substrate 11 using CVD.

[0148] As shown in FIG. 23, the silicon nitride film 13 present in thecapacitor area is removed using PEP and RIE.

[0149] As shown in FIG. 24, a tungsten nitride film (WN) 14 as adiffusion prevention film (barrier metal) is formed on the siliconnitride film 13 and in the capacitor area using sputtering. A capacitorinsulating film (e.g., Ta₂O₅) 15 is formed on the tungsten nitride film14 using sputtering. A tungsten nitride film 16 as a diffusionprevention film (barrier metal) is formed on the capacitor insulatingfilm 15 using sputtering.

[0150] A silicon nitride film 17 is formed on the tungsten nitride film16 using CVD. The silicon nitride film 17, tungsten nitride film 16,capacitor insulating film 15, and tungsten nitride film 14 aresequentially etched using PEP and RIE. Etching is performed such thatthe tungsten nitride film 14, capacitor insulating film 15, tungstennitride film 16, and silicon nitride film 17 remain in at least thecapacitor area.

[0151] As shown in FIG. 26, a silicon oxide film (interlevel insulatingfilm) 18 is formed on the silicon nitride films 13 and 17 using CVD.Subsequently, a silicon nitride film 19 as an etching stopper is formedon the silicon oxide film 18 using CVD. A silicon oxide film(inter-wiring insulating film) 20 is formed on the silicon nitride film19 using CVD. A silicon nitride film 21 as a CMP stopper is formed onthe silicon oxide film 20 using CVD.

[0152] Then, the second electrode of the MIM capacitor is formed by thedual damascene process.

[0153] For example, a trench as a wiring groove is formed in the siliconnitride film 21 and silicon oxide film 20 using PEP and RIE. In etchingthe silicon oxide film 20, the silicon nitride film 19 functions as aRIE etching stopper. The trench includes a wiring/pad portion andcapacitor electrode portion, and the capacitor electrode portion has,e.g., a matrix-like layout.

[0154] Then, trenches as via holes are formed in the silicon nitridefilm 19 and silicon oxide film 18 using PEP and RIE. In etching thesilicon oxide film 18, the silicon nitride films 13 and 17 function asRIE etching stoppers.

[0155] Note that the trench shape at the capacitor electrode portion isnot limited to the matrix shape, and may be, e.g., a drainboard shape(or ladder shape) as shown in FIG. 13, or a comb shape as shown in FIG.14 or 15.

[0156] The silicon nitride films 13 and 17 at the bottoms of thetrenches are etched to expose part of the metal material 12 and part ofthe tungsten nitride film 16.

[0157] Thereafter, metal materials (e.g., Cu) 22A and 22B for completelyfilling the trenches are formed by plating. Note that a barrier metalsuch as TaN may be formed on the inner surface of the trench before themetal materials 22A and 22B are formed.

[0158] The metal materials 22A and 22B are polished using CMP to leavethem in the trenches. At this time, the silicon nitride film 21functions as a CMP stopper.

[0159] By these steps, the MIM capacitor in FIG. 21 is completed.

[0160] According to this manufacturing method, when the damasceneprocess (CMP process) is adopted, and a metal material such as Cu(copper) having a large diffusion coefficient is used as a wiringmaterial, first, the metal material (capacitor electrode) can be formedinto, e.g., a matrix shape to prevent dishing. Second, diffusionprevention films which directly sandwich a capacitor insulating film canbe formed to prevent metal atoms from diffusing into the capacitorinsulating film during the manufacturing process. Third, the diffusionprevention film functions as a capacitor electrode, so the capacitorarea does not decrease (capacitor capacity can increase regardless ofthe wiring rule) even if the metal material is formed into a matrixshape in order to prevent dishing. Fourth, the manufacturing process issimplified because the tungsten nitride film 14 is processed by RIEtogether with the silicon nitride film 17, tungsten nitride film 16, andcapacitor insulating film 15. Fifth, the metal material (e.g., Cu) isnot exposed in patterning the capacitor, so that contamination by metalatoms can be avoided.

[0161]FIG. 28 shows the fourth embodiment of a MIM capacitor accordingto the present invention.

[0162] Compared to the embodiment in FIG. 21, the device structure ofthe fourth embodiment is characterized in that a tungsten nitride film14, capacitor insulating film 15, tungsten nitride film 16, and siliconnitride film 17 fall within the groove of a silicon nitride film 13.

[0163] The detailed device structure will be explained.

[0164] For example, a matrix-like trench is formed in a semiconductorsubstrate (e.g., silicon substrate) 11. The trench is filled with ametal material 12, e.g., Cu (copper) having a low resistance and largediffusion coefficient. The metal material 12 filled in the trench of thesemiconductor substrate 11 serves as the first electrode of the MIMcapacitor.

[0165] The shape of the first electrode of the MIM capacitor is set to,e.g., a matrix, drainboard (or ladder), or comb shape.

[0166] A silicon nitride film (SiN) 13 is formed on the semiconductorsubstrate 11 except for the capacitor area of the MIM capacitor. Thecapacitor area is a groove surrounded by the wall of the silicon nitridefilm 13. In the capacitor area, a tungsten nitride film (WN) 14 isformed. The tungsten nitride film 14 completely falls within thecapacitor area.

[0167] The tungsten nitride film 14 functions as a diffusion preventionfilm against the metal material (e.g., Cu) 12. At the same time, thetungsten nitride film 14 is formed on the matrix-like first electrode toincrease the capacitor area. A capacitor insulating film (e.g., Ta₂O₅)15 is formed on the tungsten nitride film 14.

[0168] A tungsten nitride film (WN) 16 is formed on the capacitorinsulating film 15. The tungsten nitride film 16 functions as adiffusion prevention film against a metal material (e.g., Cu) serving asthe second electrode (to be described later) of the MIM capacitor. Inaddition, the tungsten nitride film 16 is formed below the matrix-likesecond electrode (to be described later) to increase the capacitor area.

[0169] A silicon nitride film (SiN) 17 is formed on the tungsten nitridefilm 16. The silicon nitride film 17 functions as a stopper togetherwith the silicon nitride film 13 in etching (in trench formation)(details of which will be explained in a description of themanufacturing method).

[0170] Note that the tungsten nitride films 14 and 16, and capacitorinsulating film 15 have the same pattern.

[0171] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilms 13 and 17, and a silicon nitride film 19 is formed on the siliconoxide film 18. The silicon nitride film 19 functions as a stopper intrench formation by the dual damascene process. A silicon oxide film(SiO₂) 20 is formed on the silicon nitride film 19, and a siliconnitride film 21 is formed on the silicon oxide film 20. The siliconnitride film 21 functions as a stopper in the CMP (Chemical MechanicalPolishing) process.

[0172] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches as via holes reaching the tungstennitride film 16 and metal material (e.g., Cu) 12 are formed in thesilicon oxide film 18 and silicon nitride film 13. These trenches arefilled with metal materials 22A and 22B, e.g., Cu (copper) having a lowresistance and large diffusion coefficient. The metal material 22Afilled in the trench serves as the second electrode of the MIMcapacitor.

[0173] In this structure, the first and second electrodes of the MIMcapacitor are formed into a shape such as a matrix, drainboard (orladder), or comb shape in which dishing hardly occurs.

[0174] When the first and second electrodes of the MIM capacitor aremade of a metal material (e.g., Cu) having a large diffusioncoefficient, a plate-like diffusion prevention film (e.g., tungstennitride film 14) in contact with the first electrode, and a plate-likediffusion prevention film (e.g., tungsten nitride film 16) in contactwith the second electrode are formed. These diffusion prevention filmsalso increase the capacitor area of the MIM capacitor.

[0175] The capacitor insulating film (e.g., Ta₂O₅) 15 is sandwichedbetween the two diffusion prevention films, and does not directlycontact the metal material (e.g., Cu) having a large diffusioncoefficient.

[0176] The leakage current can be reduced without contaminating thecapacitor insulating film by the metal material which has a largediffusion coefficient and forms the electrode of the MIM capacitor.Accordingly, a high-performance MIM capacitor can be provided.

[0177] The manufacturing method of the MIM capacitor in FIG. 28 will beexplained.

[0178] As shown in FIG. 29, the first electrode of a MIM capacitor isformed in a semiconductor substrate 11 by the damascene process.

[0179] For example, a matrix-like trench is formed in the semiconductorsubstrate 11 using PEP (Photo Engraving Process) and RIE (Reactive IonEtching). A metal material (e.g., Cu) 12 for completely filling thematrix-like trench is formed using CVD. The metal material 12 ispolished using CMP to leave it in only the matrix-like trench, therebycompleting the first electrode of the MIM capacitor.

[0180] The shape of the trench (first electrode) is set to a matrixshape (FIG. 3), drainboard shape (FIG. 5), or comb shape (FIG. 6 or 7).

[0181] A silicon nitride film (diffusion prevention insulating film) 13for covering the first electrode of the MIM capacitor is formed on thesemiconductor substrate 11 using CVD.

[0182] As shown in FIG. 30, the silicon nitride film 13 present in thecapacitor area is removed using PEP and RIE.

[0183] As shown in FIG. 31, a tungsten nitride film (WN) 14 as adiffusion prevention film (barrier metal) is formed on the siliconnitride film 13 and in the capacitor area using sputtering. A capacitorinsulating film (e.g., Ta₂O₅) 15 is formed on the tungsten nitride film14 using sputtering. Subsequently, a tungsten nitride film 16 as adiffusion prevention film (barrier metal) is formed on the capacitorinsulating film 15 using sputtering. A silicon nitride film (diffusionprevention insulating film) 17 is formed on the tungsten nitride film 16using CVD.

[0184] As shown in FIG. 32, the silicon nitride film 17, tungstennitride film 16, capacitor insulating film 15, and tungsten nitride film14 are sequentially etched using PEP and RIE. Etching is performed suchthat the tungsten nitride film 14, capacitor insulating film 15,tungsten nitride film 16, and silicon nitride film 17 remain in thecapacitor area.

[0185] In the fourth embodiment, the tungsten nitride film 14, capacitorinsulating film 15, tungsten nitride film 16, and silicon nitride film17 completely fall within the capacitor area, i.e., the groove of thesilicon nitride film 13.

[0186] As shown in FIG. 33, a silicon oxide film (interlevel insulatingfilm) 18 is formed on the silicon nitride films 13 and 17 using CVD.Then, a silicon nitride film 19 as an etching stopper is formed on thesilicon oxide film 18 using CVD. A silicon oxide film (inter-wiringinsulating film) 20 is formed on the silicon nitride film 19 using CVD.A silicon nitride film 21 as a CMP stopper is formed on the siliconoxide film 20 using CVD.

[0187] After that, the second electrode of the MIM capacitor is formedby the dual damascene process.

[0188] For example, a trench as a wiring groove is formed in the siliconnitride film 21 and silicon oxide film 20 using PEP and RIE. In etchingthe silicon oxide film 20, the silicon nitride film 19 functions as aRIE etching stopper. The trench includes a wiring/pad portion andcapacitor electrode portion, and the capacitor electrode portion has,e.g., a matrix-like layout.

[0189] Further, trenches as via holes are formed in the silicon nitridefilm 19 and silicon oxide film 18 using PEP and RIE. In etching thesilicon oxide film 18, the silicon nitride films 13 and 17 function asRIE etching stoppers.

[0190] Note that the trench shape at the capacitor electrode portion isnot limited to the matrix shape, and may be, e.g., a drainboard (orladder) shape as shown in FIG. 13, or a comb shape as shown in FIG. 14or 15.

[0191] The silicon nitride films 13 and 17 at the bottoms of thetrenches are etched to expose part of the metal material 12 and part ofthe tungsten nitride film 16.

[0192] Metal materials (e.g., Cu) 22A and 22B for completely filling thetrenches are formed by plating. Note that a barrier metal such as TaNmay be formed on the inner surface of the trench before the metalmaterials 22A and 22B are formed.

[0193] The metal materials 22A and 22B are polished using CMP to leavethem in the trenches. At this time, the silicon nitride film 21functions as a CMP stopper.

[0194] By these steps, the MIM capacitor in FIG. 28 is completed.

[0195] According to this manufacturing method, when the damasceneprocess (CMP process) is adopted, and a metal material such as Cu(copper) having a large diffusion coefficient is used as a wiringmaterial, first, the metal material (capacitor electrode) can be formedinto, e.g., a matrix shape to prevent dishing. Second, diffusionprevention films which directly sandwich a capacitor insulating film canbe formed to prevent metal atoms from diffusing into the capacitorinsulating film during the manufacturing process. Third, the diffusionprevention film functions as a capacitor electrode, so the capacitorarea does not decrease (capacitor capacity can be increased regardlessof the wiring rule) even if the metal material is formed into a matrixshape in order to prevent dishing. Fourth, the manufacturing process issimplified because the tungsten nitride film 14 is processed by RIEtogether with the silicon nitride film 17, tungsten nitride film 16, andcapacitor insulating film 15.

[0196]FIG. 34 shows the fifth embodiment of a MIM capacitor according tothe present invention.

[0197] Unlike the first to fourth embodiments described above, thedevice structure of the fifth embodiment is characterized in that thecapacitor insulating film itself has a diffusion prevention functionwithout using any diffusion prevention film.

[0198] The detailed structure will be explained.

[0199] A trench is formed in a semiconductor substrate (e.g., siliconsubstrate) 11. The trench is filled with a metal material 12, e.g., Cu(copper) having a low resistance and large diffusion coefficient. Themetal material 12 filled in the trench of the semiconductor substrate 11serves as the first electrode of the MIM capacitor.

[0200] The metal material 12 formed in the capacitor area has a plateshape, whereas the metal material formed in the remaining area is setto, e.g., a matrix, drainboard (or ladder), or comb shape.

[0201] A capacitor insulating film 15 is formed on the semiconductorsubstrate 11. In the fifth embodiment, the capacitor insulating film 15is made of a material having a diffusion prevention function againstmetal atoms (e.g., Cu). Further, the capacitor insulating film 15 ismade of a material having an etching selectivity with respect to aninterlevel insulating film (silicon nitride film 17, silicon oxide films18 and 20, and the like; to be described later).

[0202] A silicon nitride film (SiN) 17 is formed on the capacitorinsulating film 15. The silicon nitride film 17 functions as a stopperin etching (in trench formation) (details of which will be explained ina description of the manufacturing method).

[0203] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilm 17, and a silicon nitride film 19 is formed on the silicon oxidefilm 18. The silicon nitride film 19 functions as a stopper in grooveformation by the dual damascene process. A silicon oxide film (SiO₂) 20is formed on the silicon nitride film 19, and a silicon nitride film 21is formed on the silicon oxide film 20. The silicon nitride film 21functions as a stopper in the CMP (Chemical Mechanical Polishing)process.

[0204] A trench as a wiring groove is formed in the silicon oxide film20 (portion above the silicon nitride film 19). Trenches as via holesreaching the capacitor insulating film 15 and metal material (e.g., Cu)12 are formed in the silicon oxide film 18 and silicon nitride film 17.These trenches are filled with metal materials 22A and 22B, e.g., Cu(copper) having a low resistance and large diffusion coefficient. Of themetal materials filled in the trench, the metal material 22A serving asthe second electrode of the MIM capacitor in the capacitor area has aplate shape.

[0205] In this structure, even when the first and second electrodes ofthe MIM capacitor are made of a metal material (e.g., Cu) having a largediffusion coefficient, the capacitor insulating film 15 itself has adiffusion prevention function. Thus, the leakage current can be reducedwithout contaminating the capacitor insulating film, and ahigh-performance MIM capacitor can be provided.

[0206] The manufacturing method of the MIM capacitor in FIG. 34 will beexplained.

[0207] As shown in FIGS. 35 and 36, the first electrode of a MIMcapacitor is formed in a semiconductor substrate 11 by the damasceneprocess.

[0208] For example, a trench is formed in the semiconductor substrate 11using PEP (Photo Engraving Process) and RIE (Reactive Ion Etching). Ametal material (e.g., Cu) 12 for completely filling the trench is formedusing CVD. The metal material 12 is polished using CMP to leave it inonly the trench, thereby completing the first electrode of the MIMcapacitor.

[0209] A capacitor insulating film 15 is formed on the semiconductorsubstrate 11 using sputtering. A silicon nitride film 17 is formed onthe capacitor insulating film 15 using CVD.

[0210] As shown in FIG. 37, a silicon oxide film (interlevel insulatingfilm) 18 is formed on the silicon nitride film 17 using CVD.

[0211] As shown in FIG. 38, a silicon nitride film 19 as an etchingstopper is formed on the silicon oxide film 18 using CVD. A siliconoxide film (inter-wiring insulating film) 20 is formed on the siliconnitride film 19 using CVD. A silicon nitride film 21 as a CMP stopper isformed on the silicon oxide film 20 using CVD.

[0212] Thereafter, the second electrode of the MIM capacitor is formedby the dual damascene process.

[0213] For example, a trench as a wiring groove is formed in the siliconnitride film 21 and silicon oxide film 20 using PEP and RIE. In etchingthe silicon oxide film 20, the silicon nitride film 19 functions as aRIE etching stopper. The trench includes a wiring/pad portion andcapacitor electrode portion, and the capacitor electrode portion has,e.g., a plate shape.

[0214] Trenches as via holes are formed in the silicon nitride film 19and silicon oxide film 18 using PEP and RIE. In etching the siliconoxide film 18, the silicon nitride film 17 functions as a RIE etchingstopper.

[0215] The silicon nitride film 17 at the bottom of the trench is etchedto expose the capacitor insulating film 15. Of the capacitor insulatingfilm 15 exposed in the trench bottom, the film 15 part in the capacitorarea is left, and the remaining film 15 part is selectively removed.

[0216] Resultantly, the capacitor insulating film 15 is exposed in thecapacitor area, while part of the metal material 12 is exposed in theremaining area.

[0217] After that, metal materials (e.g., Cu) 22A and 22B for completelyfilling the trenches are formed by plating. Note that a barrier metalsuch as TaN may be formed on the inner surface of the trench before themetal materials 22A and 22B are formed.

[0218] As shown in FIG. 39, the metal materials 22A and 22B are polishedusing CMP to leave them in the trenches. At this time, the siliconnitride film 21 functions as a CMP stopper. Note that an example of theshape of the second electrode of the MIM capacitor is one as shown inFIG. 40.

[0219] By these steps, the MIM capacitor in FIG. 34 is completed.

[0220] According to this manufacturing method, when the damasceneprocess (CMP process) and a metal material such as Cu (copper) having alarge diffusion coefficient are employed, contamination (leakagecurrent) of the capacitor insulating film 15 can be effectivelyprevented because the capacitor insulating film 15 itself has adiffusion prevention function. Since the electrode has a plate shape inthe capacitor area, a large capacitor area (large capacitor capacity)can be ensured. Since the electrode has a matrix, drainboard, or combshape in an area except for the capacitor area, dishing can beprevented. Moreover, since the capacitor insulating film 15 is made of amaterial having an etching selectivity with respect to a silicon oxidefilm and silicon nitride film, the manufacturing process is simplified.

[0221]FIG. 41 shows the sixth embodiment of a MIM capacitor according tothe present invention.

[0222] The sixth embodiment concerns an RF-CMOS device in which anRF-analog device and CMOS logic device are formed in one chip.

[0223] The device according to this embodiment is characterized in thata diffusion prevention film used for a MIM capacitor in the RF-analogarea is used as an element (or its part) in the CMOS logic area.

[0224] For example, a matrix-like trench is formed in a semiconductorsubstrate 11. The trench is filled with a metal material 12, e.g., Cu(copper) having a low resistance and large diffusion coefficient. Themetal material 12 filled in the trench of the semiconductor substrate 11serves as the first electrode of the MIM capacitor.

[0225] A silicon nitride film (SiN) 13 is formed on the semiconductorsubstrate 11 except for the capacitor area of the MIM capacitor. Thecapacitor area of the MIM capacitor is a groove surrounded by the wallof the silicon nitride film 13.

[0226] A tungsten nitride film (WN) 14 is formed in the capacitor area.The tungsten nitride film 14 functions as a diffusion prevention filmagainst the metal material (e.g., Cu) 12. At the same time, the tungstennitride film 14 is formed on the matrix-like first electrode to increasethe capacitor area.

[0227] In the sixth embodiment, a resistance element is formed using atungsten nitride film 14A in the CMOS logic area. The tungsten nitridefilm 14A is formed at the same time as, e.g., the tungsten nitride film14, and is equal in thickness to the tungsten nitride film 14.

[0228] That is, the step of forming the tungsten nitride film 14functioning as a diffusion prevention film can be executed at the sametime as the step of forming the resistance element (tungsten nitridefilm 14A) in the CMOS logic area. In manufacturing a device according tothe present invention, the number of steps does not substantiallyincrease from the conventional number of steps, and an increase inmanufacturing cost can be prevented.

[0229] In this embodiment, the tungsten nitride films 14A and 14 aresimultaneously formed and are equal in thickness. However, the tungstennitride film 14A may be formed from a stacked layer of the tungstennitride films 14 and 16.

[0230] A capacitor insulating film (e.g., Ta₂O₅) 15 is formed on thetungsten nitride film 14. A tungsten nitride film (WN) 16 is formed onthe capacitor insulating film 15. The tungsten nitride film 16 functionsas a diffusion prevention film against a metal material (e.g., Cu)serving as the second electrode (to be described later) of the MIMcapacitor. In addition, the tungsten nitride film 16 is formed below thematrix-like second electrode (to be described later) to increase thecapacitor area.

[0231] A silicon nitride film (SiN) 17 is formed on the tungsten nitridefilm 16. The silicon nitride film 17 functions as a stopper togetherwith the silicon nitride film 13 in etching (i.e., in trench formation).

[0232] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilms 13 and 17, and a silicon nitride film 19 is formed on the siliconoxide film 18. The silicon nitride film 19 functions as a stopper intrench formation by the dual damascene process. A silicon oxide film(SiO₂) 20 is formed on the silicon nitride film 19, and a siliconnitride film 21 is formed on the silicon oxide film 20. The siliconnitride film 21 functions as a stopper in the CMP (Chemical MechanicalPolishing) process.

[0233] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches (via holes) reaching the tungstennitride films 14A and 16, and metal material (e.g., Cu) 12 are formed inthe silicon oxide film 18 and silicon nitride film 13. These trenchesare filled with metal materials 22A, 22B, 22C, and 22D, e.g., Cu(copper) having a low resistance and large diffusion coefficient.

[0234] The metal material 22A filled in the trench serves as the secondelectrode of the MIM capacitor. The metal materials 22C and 22D filledin the trenches in the CMOS logic area serve as the electrodes of theresistance element (tungsten nitride film) 14A.

[0235] Note that the sixth embodiment adopts a matrix shape as thelayouts of the first and second electrodes of the MIM capacitor in orderto prevent dishing in the damascene process (CMP process). As long asthe structure can prevent dishing, the trench shape is not limited tothe matrix shape, and may be a drainboard (or ladder) or comb shape.

[0236] In this device structure, when the first and second electrodes ofthe MIM capacitor are made of a metal material (e.g., Cu) having a largediffusion coefficient, a plate-like diffusion prevention film (e.g.,tungsten nitride film 14) in contact with the first electrode, and aplate-like diffusion prevention film (e.g., tungsten nitride film 16) incontact with the second electrode are formed. These diffusion preventionfilms also increase the capacitor area of the MIM capacitor.

[0237] The capacitor insulating film (e.g., Ta₂O₅) 15 is sandwichedbetween the two diffusion prevention films, and does not directlycontact the metal material (e.g., Cu) having a large diffusioncoefficient.

[0238] The leakage current can be reduced without contaminating thecapacitor insulating film by the metal material which has a largediffusion coefficient and forms the electrode of the MIM capacitor. Ahigh-performance MIM capacitor can, therefore, be provided.

[0239] The sixth embodiment uses as an element (resistance element inthis embodiment) in the CMOS logic area at least one of the diffusionprevention films 14 and 16 used for the MIM capacitor in the RF-analogarea. The step of forming the tungsten nitride films 14 and 16functioning as diffusion prevention films can be done at the same timeas the step of forming an element (resistance element in thisembodiment) in the CMOS logic area. Consequently, a device according tothe present invention can be manufactured without increasing the numberof manufacturing steps, and an increase in manufacturing cost can besuppressed.

[0240]FIG. 42 shows the seventh embodiment of a MIM capacitor accordingto the present invention. FIG. 43 is a sectional view taken along theline XLIII-XLIII in FIG. 42.

[0241] The MIM capacitor of this embodiment is a modification of the MIMcapacitor of the first embodiment. The MIM capacitor of the seventhembodiment is different from that of the first embodiment in that thefirst electrode (first electrode 12) of the MIM capacitor is formed notin a semi-conductor substrate 11 but in an insulating film (e.g.,interlevel insulating film) 23 on the semiconductor substrate 11.

[0242] By forming the MIM capacitor on the insulating film 23 on thesemiconductor substrate 11, an element (e.g., MOS transistor) other thanthe MIM capacitor can be formed immediately below the insulating film23. In other words, three-dimensionally arranging elements enablesarranging elements on one chip at high density.

[0243]FIG. 44 shows the eighth embodiment of a MIM capacitor accordingto the present invention.

[0244] This embodiment is an application of a MIM capacitor according tothe seventh embodiment.

[0245] The device according to the eighth embodiment is characterized inthat the first electrode of the MIM capacitor is formed in an interlevelinsulating film, and a MOS transistor is formed immediately below theinterlevel insulating film.

[0246] Source and drain regions 24 of the MOS transistor are formed inthe surface region of a semiconductor substrate 11. A gate electrode 26is formed via a gate insulating film 25 in a channel region between thesource and drain regions 24. An insulating film 27 which completelycovers the MOS transistor is formed on the MOS transistor.

[0247] A silicon nitride film 28 as an etching stopper is formed on theinsulating film 27. An interlevel insulating film 23 is formed on thesilicon nitride film 28. A silicon nitride film 13 as a mask member oretching stopper is formed on the interlevel insulating film 23.

[0248] For example, a matrix-like trench is formed in the interlevelinsulating film 23. The trench is filled with a metal material 12, e.g.,Cu (copper) having a low resistance and large diffusion coefficient. Themetal material 12 filled in the trench of the interlevel insulating film23 serves as the first electrode of the MIM capacitor.

[0249] For example, a wiring trench is formed in the interlevelinsulating film 23. The trench is filled with a metal material 29, e.g.,Cu (copper) having a low resistance and large diffusion coefficient.

[0250] The silicon nitride film (SiN) 13 is formed on the interlevelinsulating film 23 except for the capacitor area of the MIM capacitor.The capacitor area of the MIM capacitor is a groove surrounded by thewall of the silicon nitride film 13.

[0251] In the capacitor area, a tungsten nitride film (WN) 14 is formed.The tungsten nitride film 14 functions as a diffusion prevention filmagainst the metal material (e.g., Cu) 12. At the same time, the tungstennitride film 14 is formed on the matrix-like first electrode to increasethe capacitor area.

[0252] A capacitor insulating film (e.g., Ta₂O₅) 15 is formed on thetungsten nitride film 14. A tungsten nitride film (WN) 16 is formed onthe capacitor insulating film 15. The tungsten nitride film 16 functionsas a diffusion prevention film against a metal material (e.g., Cu)serving as the second electrode (to be described later) of the MIMcapacitor. In addition, the tungsten nitride film 16 is formed below thematrix-like second electrode (to be described later) to increase thecapacitor area.

[0253] A silicon nitride film (SiN) 17 is formed on the tungsten nitridefilm 16. The silicon nitride film 17 functions as a stopper togetherwith the silicon nitride film 13 in etching (in trench formation).

[0254] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilms 13 and 17, and a silicon nitride film 19 is formed on the siliconoxide film 18. The silicon nitride film 19 functions as a stopper intrench formation by the dual damascene process. A silicon oxide film(SiO₂) 20 is formed on the silicon nitride film 19, and a siliconnitride film 21 is formed on the silicon oxide film 20. The siliconnitride film 21 functions as a stopper in the CMP (Chemical MechanicalPolishing) process.

[0255] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches (via holes) reaching the tungstennitride film 16 and metal material (e.g., Cu) 12 are formed in thesilicon oxide film 18 and silicon nitride film 13. These trenches arefilled with metal materials 22A and 22B, e.g., Cu (copper) having a lowresistance and large diffusion coefficient. The metal material 22Afilled in the trench serves as the second electrode of the MIMcapacitor.

[0256] In this device structure, when the first and second electrodes ofthe MIM capacitor are made of a metal material having a large diffusioncoefficient, a plate-like diffusion prevention film in contact with thefirst electrode, and a plate-like diffusion prevention film in contactwith the second electrode are formed. The leakage current can be reducedwithout contaminating the capacitor insulating film by the metalmaterial forming the electrode of the MIM capacitor. A high-performanceMIM capacitor can be provided.

[0257] In the eighth embodiment, the MOS transistor is formedimmediately below the MIM capacitor. In this manner, the MIM capacitoris formed on the interlevel insulating film on the semiconductorsubstrate 11, whereas an element (e.g., MOS transistor) other than theMIM capacitor is formed immediately below the interlevel insulatingfilm. Elements can be three-dimensionally arranged in one chip, whichcontributes to high element density.

[0258] Further, a general wiring line is formed in the interlevelinsulating film 23 in addition to the electrode of the MIM capacitor. Inother words, both the electrode of the MIM capacitor and the generalwiring line are formed from the same metal material (e.g., Cu).Therefore, the present invention is optimal for a device having amultilayered wiring structure.

[0259] In the eighth embodiment, the MIM capacitor and MOS transistorare arranged very close to each other. This arrangement requires ameasure for preventing interference between a signal supplied to theelectrode of the MIM capacitor and a signal supplied to the gateelectrode of the MOS transistor.

[0260] For example, if the frequency of a signal supplied to theelectrode of the MIM capacitor and that of a signal supplied to the gateelectrode of the MOS transistor are different less than 50 times, thetwo signals do not interfere with each other. In this case, the devicestructure of the eighth embodiment is very effective.

[0261] If the frequency of a signal supplied to the electrode of the MIMcapacitor and that of a signal supplied to the gate electrode of the MOStransistor are different 50 times or more, the two signals interferewith each other. In this case, the device structure of the eighthembodiment must be improved.

[0262]FIG. 45 shows the ninth embodiment of a MIM capacitor according tothe present invention.

[0263] The ninth embodiment is an improvement of the MIM capacitoraccording to the eighth embodiment. The MIM capacitor of the ninthembodiment has a device structure in which, even when the frequency of asignal supplied to the electrode of the MIM capacitor and that of asignal supplied to the gate electrode of a MOS transistor are different50 times or more, the two signals do not interfere with each other.

[0264] In short, the device according to this embodiment ischaracterized in that a shield line is interposed between a MIMcapacitor and a MOS transistor arranged vertically adjacent to eachother. Since the shield line is fixed to a predetermined potential(e.g., ground potential), a signal supplied to the electrode of the MIMcapacitor and a signal supplied to the gate electrode of the MOStransistor do not interfere with each other.

[0265] The detailed device structure will be explained.

[0266] Similar to the device in the eighth embodiment, a MOS transistoris formed in the surface region of a semiconductor substrate 11. Aninsulating film 27 is formed on the MOS transistor to completely coverit. An insulating film 31 and silicon nitride film 32 are formed on theinsulating film 27.

[0267] A shield line 30A is formed in a trench formed in the insulatingfilm 31. Similarly, a general wiring line (signal line, electrical line,or the like) 30B is formed in a trench formed in the insulating film 31.

[0268] An interlevel insulating film 33 is formed on the shield line 30Aand general wiring line 30B. A silicon nitride film 28 as an etchingstopper is formed on the insulating film 33. An interlevel insulatingfilm 23 is formed on the silicon nitride film 28. A silicon nitride film13 as a mask member or etching stopper is formed on the interlevelinsulating film 23.

[0269] For example, a matrix-like trench is formed in the interlevelinsulating film 23. The trench is filled with a metal material 12, e.g.,Cu (copper) having a low resistance and large diffusion coefficient. Themetal material 12 filled in the trench of the interlevel insulating film23 serves as the first electrode of the MIM capacitor.

[0270] For example, a trench for a general wiring line is formed in theinterlevel insulating film 23. The trench is filled with a metalmaterial 29, e.g., Cu (copper) having a low resistance and largediffusion coefficient.

[0271] The silicon nitride film (SiN) 13 is formed on the interlevelinsulating film 23 except for the capacitor area of the MIM capacitor.The capacitor area of the MIM capacitor is a groove surrounded by thewall of the silicon nitride film 13.

[0272] A tungsten nitride film (WN) 14 is formed in the capacitor area.The tungsten nitride film 14 functions as a diffusion prevention filmagainst the metal material (e.g., Cu) 12. At the same time, the tungstennitride film 14 is formed on the matrix-like first electrode to increasethe capacitor area.

[0273] A capacitor insulating film (e.g., Ta₂O₅) 15 is formed on thetungsten nitride film 14. A tungsten nitride film (WN) 16 is formed onthe capacitor insulating film 15. The tungsten nitride film 16 functionsas a diffusion prevention film against a metal material (e.g., Cu)serving as the second electrode (to be described later) of the MIMcapacitor. In addition, the tungsten nitride film 16 is formed below thematrix-like second electrode (to be described later) to increase thecapacitor area.

[0274] A silicon nitride film (SiN) 17 is formed on the tungsten nitridefilm 16. The silicon nitride film 17 functions as a stopper togetherwith the silicon nitride film 13 in etching (in trench formation).

[0275] A silicon oxide film (SiO₂) 18 is formed on the silicon nitridefilms 13 and 17, and a silicon nitride film 19 is formed on the siliconoxide film 18. The silicon nitride film 19 functions as a stopper intrench formation by the dual damascene process. A silicon oxide film(SiO₂) 20 is formed on the silicon nitride film 19, and a siliconnitride film 21 is formed on the silicon oxide film 20. The siliconnitride film 21 functions as a stopper in the CMP (Chemical MechanicalPolishing) process.

[0276] For example, a matrix-like trench, and a trench for wiring/padportions are formed in the silicon oxide film 20 (portion above thesilicon nitride film 19). Trenches (via holes) extending to the tungstennitride film 16 and metal material (e.g., Cu) 12 are formed in thesilicon oxide film 18 and silicon nitride film 13. These trenches arefilled with metal materials 22A and 22B, e.g., Cu (copper) having a lowresistance and large diffusion coefficient. The metal material 22Afilled in the trench serves as the second electrode of the MIMcapacitor.

[0277] In this device structure, when the first and second electrodes ofthe MIM capacitor are made of a metal material having a large diffusioncoefficient, a plate-like diffusion prevention film in contact with thefirst electrode, and a plate-like diffusion prevention film in contactwith the second electrode are formed. The leakage current can be reducedwithout contaminating the capacitor insulating film by the metalmaterial forming the electrode of the MIM capacitor. Hence, ahigh-performance MIM capacitor can be provided.

[0278] In the ninth embodiment, the MOS transistor is formed immediatelybelow the MIM capacitor. In this way, the MIM capacitor is formed on theinterlevel insulating film on the semiconductor substrate 11, whereas anelement (e.g., MOS transistor) other than the MIM capacitor is formedimmediately below the interlevel insulating film. Elements can bethree-dimensionally arranged in one chip, which contributes to highelement density.

[0279] A general wiring line is formed in the interlevel insulating film23 in addition to the electrode of the MIM capacitor. In other words,both the electrode of the MIM capacitor and the general wiring line areformed from the same metal material (e.g., Cu). The present inventionis, therefore, best suited to a device having a multilayered wiringstructure.

[0280] In the ninth embodiment, the shield line is interposed betweenthe MIM capacitor and the MOS transistor. Since the shield line is fixedto a predetermined potential (e.g., ground potential), a signal suppliedto the electrode of the MIM capacitor and a signal supplied to the gateelectrode of the MOS transistor do not interfere with each other.

[0281] Accordingly, this embodiment enables normal operation even whenthe frequency of a signal supplied to the electrode of the MIM capacitorand that of a signal supplied to the gate electrode of a MOS transistorare different 50 times or more.

[0282] As has been described above, according to the present invention,when the damascene process (CMP process) is adopted, and a metalmaterial such as Cu (copper) having a large diffusion coefficient isused as a wiring material, dishing can be prevented by forming the metalmaterial (capacitor electrode) into, e.g., a matrix shape. If diffusionprevention films for directly sandwiching a capacitor insulating filmare formed, or the capacitor insulating film itself has a diffusionprevention function, metal atoms can be prevented from diffusing intothe capacitor insulating film during the manufacturing process. If thediffusion prevention film functions as a capacitor electrode, thecapacitor area does not decrease (capacitor capacity can be increasedregardless of the wiring rule) even when the metal material is formedinto a matrix shape in order to prevent dishing. Since the metalmaterial (e.g., Cu) is not exposed in patterning the capacitor,contamination by metal atoms can be avoided. The capacitor structure isflat, which is advantageous for obtaining high reliability.

[0283] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A MIM capacitor comprising: first and secondelectrodes formed from a metal material; a capacitor insulating film; afirst diffusion prevention film interposed between said capacitorinsulating film and said first electrode to prevent diffusion of atomsconstituting the metal material; and a second diffusion prevention filminterposed between said capacitor insulating film and said secondelectrode to prevent diffusion of atoms constituting the metal material.2. The MIM capacitor according to claim 1 , wherein a shape of saidfirst and second electrodes is one of shapes including matrix,drainboard, and comb shapes other than a rectangular shape.
 3. The MIMcapacitor according to claim 1 , wherein said first electrode is filledin a trench in a semiconductor substrate and has a flat surface, andsaid second electrode is filled in a trench in an insulating film on thesemiconductor substrate and has a flat surface.
 4. The MIM capacitoraccording to claim 1 , wherein said first and second diffusionprevention films include metal nitride films.
 5. The MIM capacitoraccording to claim 1 , wherein said first and second diffusionprevention films consist of one member selected from the groupconsisting of Ti, TiN, TiSiN, Ta, TaN, TaC, TaSiN, TaCeO₂, Ir₄₆Ta₅₄, W,WN, W₂N, W₆₄B₂₀N₁₆, W₂₃B₄₉N₂₈, and W₄₇Si₉N₄₄.
 6. The MIM capacitoraccording to claim 1 , wherein the metal material includes Cu.
 7. TheMIM capacitor according to claim 1 , further comprising an insulatinglayer having an opening on said first electrode; wherein said firstdiffusion prevention film is filled in the opening of said insulatinglayer, and said capacitor insulating film and said second diffusionprevention film are formed on said first diffusion prevention film. 8.The MIM capacitor according to claim 7 , wherein ends of said capacitorinsulating film and said second diffusion prevention film overlap saidinsulating layer.
 9. The MIM capacitor according to claim 8 , furthercomprising a silicon nitride film formed on said second diffusionprevention film.
 10. The MIM capacitor according to claim 1 , whereinsaid first diffusion prevention film is formed on said first electrode,said capacitor insulating film is formed on said first diffusionprevention film, said second diffusion prevention film is formed on saidcapacitor insulating film, and said first and second diffusionprevention films and said capacitor insulating film are covered by asilicon nitride film.
 11. The MIM capacitor according to claim 1 ,further comprising an insulating layer having an opening on said firstelectrode; wherein said first and second diffusion prevention films andsaid capacitor insulating film are formed in the opening of saidinsulating layer.
 12. The MIM capacitor according to claim 11 , whereinends of said first and second diffusion prevention films and saidcapacitor insulating film overlap said insulating layer.
 13. The MIMcapacitor according to claim 12 , further comprising a silicon nitridefilm formed on said second diffusion prevention film.
 14. The MIMcapacitor according to claim 1 , further comprising an insulating layerhaving an opening on said first electrode; wherein said first and seconddiffusion prevention films and said capacitor insulating film are formedin the opening of said insulating layer, and are separated from saidinsulating layer.
 15. The MIM capacitor according to claim 14 , furthercomprising a silicon nitride film formed on said second diffusionprevention film.
 16. The MIM capacitor according to claim 1 , furthercomprising a resistance element formed from the same material as amaterial forming at least either one of said first and second diffusionprevention films.
 17. The MIM capacitor according to claim 16 , whereinsaid resistance element is formed in a CMOS logic area.
 18. The MIMcapacitor according to claim 1 , wherein said first electrode is filledin a trench in a first insulating layer above a semiconductor substrate,said second electrode is filled in a trench in a second insulating layerabove the first insulating layer, and said first and second insulatinglayers have flat surfaces.
 19. The MIM capacitor according to claim 18 ,further comprising a MOS transistor formed immediately below said firstelectrode.
 20. The MIM capacitor according to claim 19 , wherein afrequency of a signal supplied to said first and second electrodes and afrequency of a signal supplied to said MOS transistor are different lessthan 50 times.
 21. The MIM capacitor according to claim 19 , furthercomprising a shield line which is formed between said first electrodeand said MOS transistor, and set to a predetermined potential.
 22. TheMIM capacitor according to claim 21 , wherein the predeterminedpotential includes a ground potential.
 23. The MIM capacitor accordingto claim 21 , wherein a frequency of a signal supplied to said first andsecond electrodes and a frequency of a signal supplied to said MOStransistor are different not less than 50 times.
 24. A MIM capacitorcomprising: first and second electrodes formed from a metal material;and a capacitor insulating film which is interposed between said firstand second electrodes and has a function of preventing diffusion of themetal material.
 25. The MIM capacitor according to claim 24 , whereinsaid second electrode is filled in a trench formed in an interlevelinsulating film, and said capacitor insulating film has an etchingselectivity with respect to the interlevel insulating film.
 26. The MIMcapacitor according to claim 24 , wherein said first electrode is filledin a trench in a semiconductor substrate and has a flat surface, andsaid second electrode is filled in a trench in an interlevel insulatingfilm and has a flat surface.
 27. The MIM capacitor according to claim 24, wherein the metal material includes Cu.
 28. A manufacturing method ofa MIM capacitor comprising the steps of: forming a first electrode froma metal material by a damascene process; forming on the first electrodea first insulating film having a function of preventing diffusion of themetal material; removing part of the first insulating film to use thepart as a capacitor area; forming in the capacitor area a firstdiffusion prevention film having a function of preventing diffusion ofthe metal material; forming on the first diffusion prevention film acapacitor insulating film, a second diffusion prevention film having afunction of preventing diffusion of the metal material, and a secondinsulating film having the same function as the first insulating film;forming an interlevel insulating film on the first and second insulatingfilms; forming using the damascene process trenches reaching the firstelectrode and the second diffusion prevention film in the interlevelinsulating film and the first and second insulating films; and fillingthe metal material in the trenches to form a wiring line connected tothe first electrode and a second electrode connected to the seconddiffusion prevention film.
 29. The method according to claim 28 ,wherein the first diffusion prevention film is formed by sputtering ametal nitride film and then polishing the metal nitride film by CMP, andthe capacitor insulating film, the second diffusion prevention film, andthe second insulating film are successively processed by PEP and RIE.30. The method according to claim 28 , wherein the first diffusionprevention film, the capacitor insulating film, the second diffusionprevention film, and the second insulating film are successivelyprocessed by PEP and RIE, and ends of the first diffusion preventionfilm, the capacitor insulating film, the second diffusion preventionfilm, and the second insulating film overlap the first insulating film31. The method according to claim 28 , wherein the first diffusionprevention film, the capacitor insulating film, the second diffusionprevention film, and the second insulating film are successivelyprocessed by PEP and RIE, and ends of the first diffusion preventionfilm, the capacitor insulating film, the second diffusion preventionfilm, and the second insulating film fall within the capacitor area. 32.A manufacturing method of a MIM capacitor comprising the steps of:forming a first electrode from a metal material by a damascene process;forming on the first electrode in a capacitor area a first diffusionprevention film having a function of preventing diffusion of the metalmaterial, a capacitor insulating film, and a second diffusion preventionfilm having a function of preventing diffusion of the metal material;forming a diffusion prevention insulating film having a function ofpreventing diffusion of the metal material on the second diffusionprevention film and the first electrode; forming an interlevelinsulating film on the diffusion prevention insulating film; formingusing the damascene process trenches reaching the first electrode andthe second diffusion prevention film in the interlevel insulating filmand the diffusion prevention insulating film; and filling the metalmaterial in the trenches to form a wiring line connected to the firstelectrode and a second electrode connected to the second diffusionprevention film.